1. Field of the Invention
This invention relates to an electronic circuit and, more particularly, to an output driver circuit which produces relatively constant output logic levels between logic transitions despite process variations and changes in temperature.
2. Description of the Related Art
The form and function of emitter-coupled logic ("ECL") is generally well known. Typical ECL involves a bipolar form of logic, whereby the bipolar transistors are arranged so that they do not generally operate at saturation. ECL enjoys a high input impedance, rapid switching speed and low output impedance compared to other logic families. The ECL V.sub.DD and V.sub.EE conductors have traditionally been powered from a negative power supply, where V.sub.DD is grounded. In more recent designs, however, ECL is often used with a positive power supply. In this instance, V.sub.DD is generally set at a positive voltage and V.sub.EE is tied to ground. Positive ECL designs are often times referred to as positive- or pseudo-ECL ("PECL"). A benefit of PECL is its compatibility with standard logic supplies, such as those found in metal oxide semiconductors ("MOS") technology.
As clock speeds rise beyond 100 MHz, the advantages of using PECL become more obvious. For example, PECL can be employed within an output driver circuit to produce high speed output signals. The speed of those signals make them well suited as a clocking source or as serial link transmitted signals, if applied in the complementary form.
A clocking signal or a transmission signal must switch rapidly in modern computer and/or communication systems. Using a communication system as an example, a PECL driver is well suited for transferring ECL complementary (i.e., hereinafter "differential") outputs across a transmission medium such as a high-speed serial link comprising fiber, coax, or twisted pair. A CY7B923 transmitter obtainable from Cypress Semiconductor Corp., includes a PECL output driver capable of transferring data over a serial link at rates exceeding 160 Mbits/second.
FIG. 1 depicts a typical communication system linked by a serial bus (i.e., serial link) which is driven by a high speed PECL driver. Differential signals (OUTA and OUTA') output from transmitter 12 of communication system 10 are less susceptible to ground noise problems than, for example, single-ended MOS outputs since noise in differential PECL signals exists on both signals and becomes "common-mode". Common-mode noise is known to be more easily removable than many other types of noise. In addition, output driver 14 within transmitter 12 produces less noise as seen by the power supply. Namely, when one output drive transistor is on, the other output driver transistor is off. This ensures a constant current supply draw regardless of which output state is being produced.
Further illustrated in FIG. 1, and forming a part of transmitter 12 is an encoder 16 which encodes parallel bytes received by transmitter 12 and converts those encoded bytes into a serial stream of bits via serializer 18. The serial bit stream is then presented in complementary form across a serial link 20. Termination resistors 22 can be coupled at or near the receiver 24. Receiver 24 can therefore de-serialize and decode the serial bit stream as shown by blocks 26 and 28.
FIG. 1 illustrates only one example in which a PECL circuit is used. However, it is understood that the speed at which the PECL output signal transitions is equally suited for any application which requires high speed switching. Therefore, the PECL circuit 29 shown in FIG. 2, while suitable as an output driver 14, is nonetheless applicable to any high speed output driver which utilizes differential output signals.
Differential binary signals are defined as the difference between two outputs at dissimilar logic values. Thus, when signal OUTA is at a logic "1" or "high" value, then output OUTA' is at a logic "0" or logic "low" value. At other times, output OUTA' is at a logic high value, while output OUTA is at a logic low value. The logic high value produced at the output of circuit 29 in FIG. 2 is often referred to as V.sub.OH, while the logic low value from circuit 29 is deemed V.sub.OL.
FIG. 2 illustrates one example of a PECL output driver 29. The performance of first and second drive transistors 31 and 33 can substantially vary depending on their operating temperature and the methodology in which they were made. For example, an increase in operating temperature will decrease the base-to-emitter forward bias voltage ("V.sub.BE ") of transistors 31 and 33. V.sub.BE is a well known parameter which typically characterizes a bipolar transistor's performance and is generally defined as a voltage, which, when exceeded, will cause current to flow from the base to the emitter and, more importantly, activation of current from the collector to the emitter. V.sub.BE can also vary based on the parameters used to fabricate transistors 31 and 33. As those parameters change, or as temperature changes, the performance of the transistors correspondingly changes as evidenced by a change in V.sub.BE. There may be numerous processing parameters which might vary to effect that change such as, for example, doping concentrations. It is generally recognized, for example, that for every 1.degree. C. increase in temperature, the forward bias voltage from the base-to-emitter (i.e., V.sub.BE) will decrease approximately 2.0 mV. A decrease in V.sub.BE will affect the performance of output driver 29.
PECL output driver 29 includes a pair of differential inputs (INA and INA') forwarded to a corresponding pair of npn bipolar transistors 35 and 37. If, for example, input INA' is at a logic high value (i.e., a voltage value which permits significant current flow from the collector to the emitter of transistor 35) then the amount of current flow will be equal to that sourced by current source 39. The sourced current is labeled I.sub.DIFF. Current I.sub.DIFF will traverse the collector and emitter of transistor 35, but will not traverse transistor 37 since the complimentary input INA is at a low logic value causing transistor 37 to remain in a "off" state. In this case the output voltage at node OUTA will be at the low logic level, while the output voltage at node OUTA' will be at the high logic level. The output logic levels are described by the following equations which clearly demonstrate the dependence of V.sub.OH and V.sub.OL on V.sub.BE : EQU V.sub.OH =V.sub.DD -V.sub.BE (eq. 1) EQU V.sub.OL =V.sub.DD -V.sub.BE I.sub.Diff (R.sub.49) (eq. 2)
Referring to FIG. 3, an improved output driver 30 is presented. Specifically, driver 30 includes not only first and second drive transistors 32 and 34, differentially coupled bipolar transistors 36 and 38, and resistor pair 50 and 54, but also includes a pair of diode-connected transistors 42 and 44, and associated resistors 46 and 48 connected in parallel between resistor pairs 50 through 56. Resistors 50, 52, 54 and 56 are shown connected between a positive power supply V.sub.DD and respective collectors of npn transistors 36 and 38. If transistor 38 is conducting, and transistor 36 is non-conducting, then current I.sub.DIFF will produce a voltage through resistor 50 and 52. If driver 30 is operating at temperatures where V.sub.BE required for significant current flow is relatively large, then the voltage developed across resistor 50 will not be sufficient to turn on the diode connected transistor 44, and the current through resistor 50 will be essentially I.sub.DIFF But as temperature rises and V.sub.BE decreases, the voltage across resistor 50 will be enough to create a current flow through resistor 54, transistor 44 and resistor 48. Accordingly, the diode-connected transistor 44 will be forward biased causing current I.sub.T to flow through resistor 54 and resistor 48. Current I.sub.T will add to current I.sub.ON through resistor 50 to equal I.sub.DIFF.
Depending on which of the differential pair of transistors 36 and 38 are on, the current through resistors 50 and 52, and 54 and 56 determine the output logic levels (V.sub.OL and V.sub.OH) at the emitter terminals of transistors 32 and 34. For example, if input INA' causes transistor 38 to turn on, then the base voltage upon transistor 32 is at a logic low level. The result of a logic low level at the base of transistor 32 is a logic level low (V.sub.OL) at output OUTA. The level of V.sub.OL is, however, dependent upon the amount of current ION through resistor 50. If the current which is diverted from one side to the other (i.e., current I.sub.T) increases, I.sub.ON will decrease. The result of a decreasing I.sub.ON is to lower the voltage across resistor 50, and thereby raise the voltage at the base of transistor 32. This results in an increase in V.sub.OL. The converse is true with respect to V.sub.OH. Specifically, an increase in I.sub.T will cause a decrease at the base of transistor 34, and therefore a decrease of V.sub.OH at output signal OUTA'. The relationship between V.sub.BE and V.sub.OH, as well as V.sub.OL for driver 30 shown in FIG. 3 is: as V.sub.BE decreases, V.sub.OH and V.sub.OL increases. However, the diverted current I.sub.T compensates for the decreasing V.sub.BE so that it will cause V.sub.OH to decrease and V.sub.OL to increase. Thus, diverting current will offset the increasing V.sub.OH.
Diverting current I.sub.T must therefore be carefully regulated to establish output high (V.sub.OH) values at or near a midscale voltage of the maximum and minimum output high values. That is, current I.sub.T must be adjusted so that V.sub.OH values fall within a specified or pre-defined maximum and minimum amounts required by the manufacturer for a particular application. For example, transmitter part no. CY7B923 requires for proper, discernible output values, that V.sub.OH maximum and minimum values fall within the range of V.sub.DD -0.83 and V.sub.DD -1.03, respectively. Likewise, the specified V.sub.OL values should not exceed the maximum of V.sub.DD -1.62 and the minimum of V.sub.DD -1.86.
While the diverting current helps compensate for a decrease in V.sub.BE by offsetting the increasing V.sub.OH, its effect on V.sub.OL is to further increase it. It is therefore necessary to utilize yet another compensating mechanism to offset the increasing V.sub.OL. To compensate for current lost through resistor 50 when transistor 38 is on and when V.sub.BE decreases, additional current must be sourced by current source 40. An increase in I.sub.DIFF dependent upon V.sub.BE is, however, difficult to achieve and implement since a temperature-compensating current source is not always accurate across the entire temperature range.
An explanation of the mechanism by which V.sub.OH and V.sub.OL is established can, alternatively, be described in a mathematical sense. If transistor 36 is off, and diverted current I.sub.T is present through a forward biased diode-connected transistor 44, then V.sub.OH is as follows: EQU V.sub.OH =V.sub.DD -V.sub.BE -I.sub.T (R.sub.54) (eq. 3)
Similarly, transistor 38 being on will produce V.sub.OL at the output of transistor 32 as follows: EQU V.sub.OL =V.sub.DD -I.sub.DIFF R.sub.52 -(I.sub.DIFF -I.sub.T)R.sub.50 -V.sub.BE (eq. 4)
From equations one and two, it is recognized that both V.sub.OH and V.sub.OL are not only dependent upon the diverted current I.sub.T, but also upon V.sub.BE of the respective output drive transistors 32 and 34. In addition, for low swing output drivers, the swing amounts may not be sufficient to turn on the diode-connected transistors 42 and 44. Yet further, the differential configuration shown in FIGS. 2 and 3 cannot compensate for single ended PECL outputs without adding deleterious compensation to the other half (second end of the complementary set). To help rectify these problems, a circuit is needed to provide better compensation for changes in V.sub.BE. It would be desirable that an improved PECL output driver be derived which does not rely upon tail current or cross coupling of the differential stage's load resistors. Furthermore, the improved output driver circuit must produce output logic levels V.sub.OL and V.sub.OH which are not dependent whatsoever upon V.sub.BE, or the need for varying a current source to compensate for changes in V.sub.BE.